1. Field of the Invention
The present invention relates to area and power management in dynamic logic. More specifically, the present invention relates to statically storing the value of dynamic signals under certain operating conditions and in selected areas of dynamic logic to reduce the overall power consumption of the design without affecting performance.
2. Description of the Related Art
High performance complementary metal-oxide semiconductor (CMOS) very large scale integrated (VLSI) circuits are increasingly using dynamic logic gates to improve circuit performance. Dynamic logic gates are fast, but require a frequent refresh to hold a logic state. Constantly switching transistors on and off to precharge and then evaluate dynamic logic gates consumes an enormous amount of power. Accordingly, because of the power and noise constraints on dynamic logic gates, many high performance CMOS VLSI are designed using conventional static logic gates outside the critical path of the logic. Static circuits hold state without a frequent refresh. Since power is consumed only when the inputs switch, static circuits consume much less power than dynamic circuits.
However, static circuits are generally slower than dynamic circuits, and mixing the two has been problematic. Static flip-flops have been used to interface dynamic logic and static logic, but this typically creates timing and performance problems due to the long setup and hold times associated with static flip-flops. In addition, static signals (i.e., non-precharged) that feed dynamic circuits also have long setup times.
Conventional static flip-flops generally have uncertainty when the flip-flops' output signals become stable. Consequently, depending on the clock rate, the time required for a conventional static flip-flop's output signals to become stable may extend into the evaluation phase of the dynamic logic gate that the static flip-flop is driving. This delay while the flip-flop's output becomes stable is the setup time. In the past, designers have accommodated the setup delay by simply operating the design at a slower clock rate, thus giving the static flip-flop adequate time to provide stable output signals to the dynamic logic gate before the dynamic logic gate enters the evaluation period. Alternatively, some designers have inserted a clock delay between a static flip-flop and the dynamic gate the flip-flop is driving, to delay the gate's evaluation phase enough to insure that the flip-flop's outputs are stable. Neither solution is practical for today's high performance circuits. The timing constraints that typical static flip-flops impose on designers trying to use them in dynamic logic is described in detail in U.S. Pat. No. 6,118,304 (hereinafter, the “Logic Synchronization Patent”), which is incorporated by reference for all purposes into this specification.
The Logic Synchronization Patent and the documents referenced therein, specifically, U.S. Pat. No. 6,066,965, entitled “Method and Apparatus for a Logic Circuit using 1 of 4 Signals” (hereinafter, “the NDL patent”) also describe the use of NDL or N-NARY dynamic logic and a novel multiphase clock scheme for logic timing and synchronization that makes extensive use of ‘time-borrowing’ to achieve the extremely fast logic required for current high-performance applications. NDL, which is part of FAST14logic technology, is a new logic family developed by Intrinsity Inc. (f/k/a EVSX Inc.), the Assignee of this application. Although, as the NDL patent details, the FAST14 logic technology includes features that cause circuits implemented in FAST14 logic (denoted as “NDL gates” or “NDL designs”) to consume much less power than traditional dual-rail dynamic logic, even highly complex NDL designs can suffer some of the power problems associated with the high switch factor of traditional dynamic logic. Consequently, designers of NDL logic circuits and systems may find it advantageous to incorporate static storage elements into their designs. For example, designers may want to use a static storage element that receives one or more 1-of-N signals from a source NDL gate and stores those signal values for multiple clock phases, until they are required to feed a destination NDL gate, rather than passing the signals through a series of dynamic buffers between the source and destination gates. Similarly, designers may want to insert static storage elements into logic areas that are dormant for specific periods of time, thus eliminating the power required to evaluate logic gates that are not in active use.
FAST14 logic elements, features, and principles that are relevant to the present invention are further described in U.S. Pat. No. 6,219,686 (Sum/HPG Adder/Subtractor Gate), U.S. Pat. No. 6,202,194 (Twizzle), U.S. Pat. No. 6,324,239 (Shifter), U.S. Pat. No. 6,269,387 (3-Stage 32-Bit Adder), and U.S. Pat. Nos. 6,367,065 and 6,259,497 (collectively, Hardware Development Language and Tools), all of which are incorporated by reference for all purposes into this specification. In addition, the present invention is related to U.S. patent application Ser. No. 10/186,770, filed on 1, Jul. 2002 now U.S. Pat. No. 6,714,045, and entitled “Static Transmission of FAST14 Logic 1-of-N Signals”, which is incorporated by reference for all purposes into this specification.